1. Field of the Invention
The present invention generally relates to a nonvolatile memory device and to a method of manufacturing the same. More particularly, the present invention generally relates to a nonvolatile memory device which exhibits favorable programming and erasing characteristics, and favorable resistance to punch-through, and to a method of manufacturing the same.
A claim of priority is made to Korean Patent Application No. 10-2004-0103102, filed Dec. 8, 2004, the disclosure of which is incorporated herein by reference.
2. Description of the Related Art
In a conventional flash memory device, the gate electrode of a memory cell is constructed of a floating gate and a control gate, where the floating gate is insulated from the control gate by a dielectric layer. More recently, nonvolatile memory devices configured with a double gate structure have been developed. Known as split-gate flash memory devices, these devices require a relatively low erasing voltage by performing an erasing operation from the floating gate to a word line.
FIG. 1 is a cross-sectional view of a conventional split-gate flash memory device. As shown, two floating gates 112 are spaced apart from each other over an active region of substrate 102, and a gate insulating layer 110 is interposed between the substrate 102 and floating gates 112. Likewise, two control gates 122 are formed above the respective floating gates 112 and the substrate 102. A source region 124 is formed in substrate 102 between two floating gates 112, and a drain region 126 is formed in substrate 102 and spaced from source region 124. As shown, a portion of the drain region 126 is overlapped by control gates 122.
The floating gates 112 and respective control gates 122 are insulated from each other by an inter-gate insulating layer 116 and a tunneling insulating layer 118. A channel region L is defined as a region formed below each pair of floating gates 112 and control gates 122.
Control gate 122 acts as a word line, i.e., connected to the word line. Drain region 126 is connected to a bit line and is used to execute data programming, erasing, and reading.
As the need for a higher memory capacity of the flash memory device increases, the size of each unit cell tends to decrease. However, in order to reduce the size of the unit cell, a length Lf of the floating gate 112 and/or a length Lc of the control gate 122 must be reduced. The result is a degradation of cell characteristics.
That is, when the length Lf is reduced, an electron storage area of the floating gate 112, which stores electrons during a programming operation, is also reduced to thereby lower programming efficiency. On the other hand, when the length Lc is reduced, the distance between the drain region 126 and source region 124 is also reduced, which disadvantageously can cause punch-through. Furthermore, when the thickness of the inter-gate insulating layer 116 is increased due to a thermal oxidation process, which is used to decrease the coupling between floating gate 112 and control gate 122 during an erasing operation, a perforation at a center portion of floating gate 112 may occur.